NOVELTY - A device comprises a substrate (200) having porous dielectric region(s), and pore sealing layer operable to seal the porous dielectric region. The pore sealing layer contains organosilane having hydrolyzable group which bonds with the porous dielectric region. The hydrolyzable group does not comprise an alkyl group.    USE - Device e.g. integrated circuits, semiconductor devices, flat panel displays, optoelectronic devices, data storage devices, magnetoelectronic devices, magnetooptic devices, molecular electronic devices, solar cells, photonic devices and packaged devices (all claimed). Can also be used as microprocessors, graphic processors, analog to digital converters, digital to analog converters, signal processors and image processors.    ADVANTAGE - The molecular self-assembly provides an improved copper interconnect integration, without dielectric loss/damage and without re-deposition of undesired material(s) removed and/or generated during the cleaning process. The interconnect formation requires the cleaning of the bottoms of via to enable excellent adhesiveness (e.g., barrier layer to underlying copper), electrical performance (e.g., low contact and/or via resistance), and reliability performance (e.g., stress migration and/or electromigration resistance). Additionally or alternatively, the materials and/or processes used to form the capping layer can be chosen to produce a capping layer is sufficiently effective in inhibiting diffusion of material used to form the electroconductive regions (e.g., copper) such that a dielectric barrier layer can be eliminated from the electronic device or reduced in thickness (with decrease in capacitance and associated benefits). In particular, the surface of the dielectric region can be functionalized to inhibit formation of the capping layer and the exposed surfaces of the electroconductive regions can be functionalized to promote adhesion of the capping layer. Eliminating the dielectric barrier layer or reducing the thickness of the dielectric barrier layer reduces capacitance, which can decrease the power consumption and/or increase speed of operation of the electronic device.    DESCRIPTION OF DRAWING(S) - The drawing shows cross-sectional view of the substrate including trenches and vias formed in a dielectric material of the substrate.    Substrate (200)    Trench (201)    Vias (202)    Dielectric material (203)    Conductive material layer (299)